Methods for forming monolithic semiconductor devices



May 23, 1967 T. MURPHY 3,321,340

METHODS FOR FORMING MONOLITHIC SEMICONDUCTOR DEVICES Original Filed Oct.20, 1961 2 Sheets-Sheet 1 :2 Fig.2.

May 23, 1967 B. T. MURPHY 3,321,340

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Do INVENTOR Bernard T Murphy ATTORNEY United States Patent 3,321,340METHODS FOR FORMING MONOLITHIC SEMICONDUCTOR DEVICES Bernard T. Murphy,Greensburg, Pa., assignor to Westinghouse Electric Corporation,Pittsburgh, Pa., a corporation of Pennsylvania Original application Oct.20, 1961, Ser. No. 146,624, now Patent No. 3,237,062, dated Feb. 22,1966. Divided and this application Nov. 17, 1965, Ser. No. 508,225 9Claims. (Cl. 148-175) This application is a division of application Ser.No. 146,624, filed Oct. 20, 1961, now Patent No. 3,237,062, issued Feb.22, 1966.

This invention relates generally to monolithic semiconductor deviceswhich provide within a unitary body of semiconductive material theelectronic function of an entire circuit of conventionallyinterconnected components. More particularly, the invention is directedto an improved structure for monolithic semiconductor devices in generaland to methods of producing monolithic semiconductor devices.

A monolithic semiconductor device, often referred to as a functionalelectronic block, incorporates within a unitary body of material all theindividual functions of the elements comprising an entire circuit suchas an amplifier, an oscillator, a multivibrator or a logic gate. In thedesign of functional electronic blocks the problem is often encounteredof providing effective electrical isolation between two or more portionsof the block except in certain desired current paths. One known methodof solving this problem which has been at least partially successful isthat of utilizing a main body of high resistivity starting material todecrease the electrical interaction between different functionalportions. More highly doped regions formed on opposite surfaces of thebody of the high resistivity material provide the functional regions.Difficulties arise because the degree of isolation is not as high as isdesired and therefore it is necessary to use a large volume of the highresistivity material thus increasing the size of the device.

It is also the case that it is desirable to decrease the saturationresistance in those portions of the block providing transistor functionsso that a sharper transistor characteristic is obtainable.Unfortunately, the prior isolation method increases the saturationresistance since a portion of the high resistivity material is withinthe transistor structure. The improvements of providing more completeisolation between different portions of the block and decreasing thesaturation resistance in the transistor portions would make thefabrication of some types of functional electronic blocks simpler andwould make possible other types which were not previously possible.

It is therefore an object of the present invention to provide improvedstructures for functional electronic blocks.

Another object is to provide improved methods for fabricating functionalelectronic blocks.

Another object is to provide structures, and a method of forming thestructures, for functional electronic blocks which provide an inherenthigh degree of electrical isolation between portions of the block.

Another object is to provide functional electronic blocks and methods ofmaking them which provide a low saturation resistance in the transistorportion.

In accordance with this invention, improved functional electronic blocksare provided having a basic structure comprising a very high resistivitymaterial (at least about 100 ohm-cm.) of a first type ofsemiconductivity having regions of low resistivity material of a secondtype of semiconductivity on one surface thereof; a layer ice of highresistivity material of said second type of semiconductivity is disposedcompletely over said one surface and other highly doped regions aredisposed thereon. In accordance with the improved method of the presentinvention, the second high resistivity layer is grown epitaxially overthe surface of the very high resistivity block having the lowresistivity portions thereon. The epitaxial layer is characterized byhaving a relatively uniform doping impurity distribution. A preferredthickness for the epitaxial layer is in the range from about 10 micronsto about 20 microns. The resistivity of the epitaxial layer ispreferably in the range of about 1 to about ohm-cm.

The present invention, both as to its organization and fabrication,together with the above-mentioned and further objects and advantagesthereof, may best be understood by reference to the followingdescription, taken in connection with the accompanying drawings, inwhich:

FIGURES 1 through 6 are cross sectional views of a generalizedfunctional electronic block at various progressive stages of fabricationin accordance with the present invention;

FIG. 7 is a plan view of a functional electronic block providing thefunction of a stroke logic element made in accordance with the presentinvention and shown as a specific application of its teachings;

FIG. 8 is a cross sectional view of the block of FIG. 7 taken along theline VIII-VIII; and,

FIG. 9 is the approximate equivalent circuit of the device of FIGS. 7and 8.

The starting point in the practice of this invention is a wafer of highresistivity semiconductor material, at least 100 ohm-cm., of aconvenient thickness for mechanical strength of about 4 mils. It isgenerally advantageous to use a wafer with p-type semiconductivity, buta wafer having n-type semiconductivity can also be used. The startingp-type wafer 10 is shown in FIG. 1 with an n-type layer 12, having asheet resistivity of about 1 to about 10 ohms per square and about 8 to10 microns deep, diffused into a select area of the surface of the wafer10 as is dictated by block design. The diffusion to provide layer 12 maybe done using a suitable n-type impurity such as phosphorous or arsenicas the diifusant and Well known oxide masking techniques. The dopinglevel at the surface of layer 12 is in the range from about 10 to about10 atoms per cubic cm. The purpose of the n-type layer 12 is to providea low resistivity collector region in a transistor structure. A p-njunction 11 is between the bulk material 10 and the n-type region 12.The region 12 has a resistivity at least about an order of magnitudeless than that of either of the layers 10 or 14.

The next step resulting in the structure shown in FIG. 2 is that ofgrowing a high resistivity n-type layer 14 on the surface of the blockusing epitaxial growth techniques. Epitaxial growth in semiconductortechnology means growth on a single crystal of material deposited fromthe vapor phase, the growth being such as to continue the originalsingle crystal structure. It is well known in semiconductor technologyand provides a means of forming a very thin layer having a high purityon a relatively impure substrate. The particular method of epitaxialgrowth used in the practice of this invention is not critical. Severalmethods are now known and others are being developed. As an example, onesuch method for epitaxial growth of silicon layers on a silicon waferinvolves a chemical disproportionating reaction involving passing ofsilicon iodide vapors over the heated wafer 10. A similar reactionpermits epitaxial growth of germanium on germanium crystals by passinggermanium iodide vapors thereover. Another method includes growth of anepitaxial layer of silicon on silicon from an atmosphere comprising amixture of hydrogen and silicon tetrachloride carried out at arelatively high temperature. Reference is made to Longini applicationSer. No. 145,- 646, filed Oct. 17, 1961, and now abandoned, and assignedto the same assignee as the present invention, for details on such aprocess.

The thickness of the epitaxial layer 14 is desirably quite small. Theepitaxial layer may contain a doping impurity and is preferably n-type.Present information indicates that the optimum thickness of this layeris in the range from about 10 microns to 20 microns. However, layersfrom a few microns to several hundred microns may be desired in somecases. The epitaxial layer may be grown only on the upper surface of thewafer 10 if desired by providing an oxide layer 16 on the sides andunderside. Wherever the epitaxially grown layer 14 contacts the bulkmaterial of wafer 10 a p-n junction 15 is formed.

The resistivity of the epitaxial layer 14 is selected to be sufficientlyhigh to provide lateral electrical isolation while not contributing toomuch to transistor saturation resistance. Hence, a design compromise ismade with a resistivity in the range from about 1 ohm-cm. to about 100ohm-cm. being generally suitable.

Next, as shown in FIG. 3, a p-type diffused layer 18 is formed in theepitaxially grown layer 14 to a thickness of about 3 to 4 microns.Diffusion may be carried out by using a suitable -p-type impurity suchas boron and known diffusion techniques. A -pn junction 19 is formedwithin the epitaxial layer 14 at the interface of the diffused layer 18.

Thereafter, an oxide mask 21 is formed on the body with openings thereinfor transistor emitter and additional areas as will be explainedsubsequently. The oxide is removed from these areas to form the desiredopenings by an oxide etching process. The opening 23 defining theemitter area is then covered with a masking material such as a wax (notshown) and the block is exposed to a silicon etch to remove about halfor a little more of the thickness of layer 18 from the surface. Thisresults in the structure appearing in FIG. 4 with the etched depressions22. Alternatively, photoresist or other masking could be used instead ofwax masking.

The block is then cleaned of wax but not oxide and the diffusion ofn-type doping material is carried out at depressions 22 and area 23 atthe same time, the diffusion producing collector and resistor contactareas 25 and 26, respectively, so that low resistivity n-type materialextends through the p-type layer 13 at depressions 22 and into then-type epitaxial layer 14. The n-type doping extends only partway intothe layer 18 at opening 23. The structure of FIG. 5 is the result withemitter 24 forming a p-n junction with layer 18.

In the generalized process for forming a functional electronic blockshown in FIGS. 1 through 5, there results a transistor portion havingregions forming the emitter 24, base 18 and collector 12 with aresistive re gion 18a of another portion of the layer 18 providing abias resistance connected to the collector 12. Therefore, a point forbias potential application exists at the extremity of the resistiveregion 18a and it is necessary that isolation be provided between thebias point and the collector region 12 except through the resistiveregion 18a. In FIG. 6 is shown the completed structure with a biascontact 27 and a collector contact 28 at opposite extremities of theresistance 18a.

In the situation as shown in the FIGS. 1 to 6 where a resistance in thep-type diffused layer runs from a positive supply contact to atransistor collector or base, a current inevitably flows into theunderlying n-type material in the vicinity of the positive supplycontact. If a contact at that point is formed simply by making contactto the p-type skin, the current flowing from the contact through thep-type skin into the n-type layer will consist of holes injected intothe n-type layer due to the forward bias across the junction. If thiswere done in the design shown here the holes would flow across thereverse biased p-n junction between the epitaxial material and the bulkmaterial as in transistor action. In that case the purpose of startingwith p-type material would be defeated since it would be just aseffective to use an ntype bulk material on which the collector contactsare formed.

However, by shorting the junction 19 below the positive supply contact27, as shown in FIG. 6, the injection of holes into the n-type epitaxiallayer 14 can be avoided. In this way, of course, the reverse bias acrossjunction 15 is effective to provide electrical isolation.

It will also be necessary to insure a similar variation of potentialwith distance along the resistor in the diffused and epitaxial layers.The relative variation of potential can readily be achieved in the finalstep of block fabrication which consists of etching resistor channelsand transistor mesas. This step is carried out using the photoresisttechniques as in present fabrication procedures. However, in this lastcase it is necessary that the etch should penetrate through the wholeepitaxial layer 14 rather than the diffused p-type layer 18 only. Inthis way the undesired paths of the n-type epitaxial layer 14 areminimized and since they will everywhere have the same width as theoverlying p-type resistors, the requirements of relative potentialvariation outlined above will be satisfied.

In the transistor portion of the new configuration it can be seen thatthe saturation resistance will be due to the contact resistance, theresistance of the n-type diffused layer 12 and the resistance of theepitaxially grown layer 14 below the emitter 24. The first two effectsare very small. The resistance of the epitaxially grown layer 14 is muchsmaller than the corresponding layer of previously constructedfunctional electronic blocks since the epitaxially grown layer 14 ismuch thinner than the corresponding layer in previous designs. Despitethe relatively high resistivity of the layer 14, the volume in thetransistor is so small that the contribution to resistance is small. Ineffect, there need be virtually no high resistivity layer in thetransistor structure. The bulk material 10 provides a support on whichthe transistor structure rests. Conductivity modulation effects resultfrom (1) the normal injection of carriers due to transistor action, (2)the fact that in saturation, the collector junction is forward biasedwhich results in the injection of holes into the collector regions.Conductivity modulation and the high conductivity diffused layersimmediately below the collector contact 28 help avoid any highresistivity effects.

The junction 15 between the n-type expitaxial layer 14 and the bulkmaterial in wafer 10 provides effective isolation between componentparts of the block. The bulk material in wafer 10 will assume the lowestpotential of any of the n-type regions above it such as the layer 12.This is necessarily so because otherwise either junction 11 or 15 wouldbe forward biased over some area resulting in a discharge through thatarea. This means that the junction 15 between the high resistivityp-type wafer 10 and the epitaxial layer 14 is in reverse bias in allother areas and the only D.C. coupling through the p-type wafer 10 isdue to leakage. A.C. coupling is reduced because of the low capacitanceof the p-n junction 15 between the two high resistivity regions of 10and 14. It can now be further reduced since there is no limitation onthe resistivity of the starting material due to transistor requirementsand the purest material obtainable can be used.

The principal source of undesirable interconnections in previousfunctional blocks is through the starting material. Interconnections ofthis type may exist in the proposed structures in the epitaxially grownlayer 14, but since this layer 14 is reduced in thickness by an order ofmagnitude below the thickness required in present blocks, theinterconnection is slight. Further reduction in current through then-type layer 14 may be made by etching away that portion of the layer 14except under the resistors such as 18a. Additional advantages of thepresent method over previous ones is that there is no need for a cavityin the starting wafer in the collector region of the transistors sincethe transistor structure is built up on just one side of the startingwafer. Another advantage is that all ohmic contacts to the device may bemade to the upper surface.

There will now be described a specific example of a device designed andfabricated in accordance with the present invention. The view of FIGS. 7and 8 shows a monolithic semiconductor device providing the function ofa stroke logic element having the approximate equivalent circuit asshown in FIG. 9. Copending application Ser. No. 140,472, filed Sept. 25,1961, now Patent 3,209,- 214, issued Sept. 28, 1965 discloses amonolithic stroke element of similar geometry without the use of anepitaxial layer. While the stroke logic element is given as a specificexample of the practice of the present invention, it is to bespecifically understood that the application of the principles of thisinvention may be made to a Wide variety of functional electronic blocksincluding amplifiers, oscillators, multivibrators and others. In anycase in which there is the necessity for isolation between two or moreportions of the block, the practice of the present invention isadvantageous. FIGS. 7 and 8 show the structure of the stroke gateincluding a layer applied by epitaxial growth. The structure comprisesgenerally a base 110 of high resistivity p-type bulk material, selectportions of n-type diffused material 112 in the bulk material base, anepitaxially grown n-type layer 114, a p-type diffused layer 118 and ann-type diffused layer 124. The conductivity types given are merely byway of example.

Input diodes are formed of what are essentially threelayer transistorstructures T and T (FIGS. 7 and 9) which have certain junctions shortedout in accordance with the teachings of referred to Patent 3,209,214.Specifically, each transistor comprises a portion of the n-typeepitaxial layer 114 as its collector, a portion of the p-type diffusedlayer 118 as its base and a region of n-type material diffused thereinas the emitter. Each of the collector regions of transistors T and T isshorted out to the base of transistor T A diffused collector region maybe used but is not essential in transistors T and T The transistorregion T is formed substantially as shown in FIGS. 1 through 6. Here,however, the collector low resistivity region 112 is enlarged to providealso an opposing surface in the output diode region D which comprisesthe p-type surface layer 118 and the n-type epitaxial layer 114 and acontact from the collector of the transistor T The resistors R1, R2 andR3 are formed in portions of the p-type layer 118. Ohmic contacts 140are provided where necessary on the device 118. As shown, the p-typelayer has been etched away except in those regions essential to thestructure. Alternatively, the p-type layer may be diffused into theepitaxial layer in a pattern only in the desired portions. To providethe circuit equivalent of FIG. 9, it is of course necessary to provide aconductive path (as by a wire or an evaporated metal layer) between theemitter 124 of T and the base 118 of T and also between the emitter of Tand the base contact of T The collector contact C and the B+ and B-contacts may be made similarly to those'in FIG. 6.

The essential operations for the fabrication of the block shown in FIGS.7 and 8 will now be given. While the following description is given forthe making of a mesa type structure wherein a continuous p-type diffusedlayer is formed which is etched away except where desired, the necessarymodifications to make a planar structure wherein the p-type diffusedlayer is formed only where desired, thus giving a planar surface, areapparent. While silicon is given as an example of the semiconductivematerial,

this choice is not critical, it is to be understood that othersemiconductor materials may also be used, such as germanium or acompound comprised of stoichiometric portions of elements of Group IIIand Group V of the Periodic Table, fo rexample, gallium, arsenide,gallium.

antimonide, gallium phosphide, indium arsenide and indium antimonide. Itwill also be understood that the device may be fabricated so that thesemiconductivity of the various regions is the reverse of that shown anddescribed previously.

There is first obtained a wafer 110 of silicon containing a suitablep-type impurity prepared by methods known to those skilled in the art.For a starting material of very high resistivity of about 5,000ohm-centimeters, the impurity level is adjusted to the appropriate levelby vapor diffusion doping. The wafer may b sliced from a crystal andpolished and etched on one side to produce a smooth surface. An oxidelayer is formed on the surface to a thickness of approximately onemicron. This may be formed by thermal oxidation of the wafer in watervapor with a silicon temperature of about 1150 C., a water bathtemperature of 90 C. and argon as a carrier gas flowing at 1 liter perminute. The oxide layer is selectively etched away using known wax orphotoresist masking techniques and hydrogen fluoride etchant, to removeoxide from those areas where it is desired to form a low resistivityn-type layer 112 as for the transistor collectors; Phosphorus is thendiffused into the exposed areas at about 1075 C. for /2 hour, with P 0as the source at about 310 C. and dry oxygen as carrier gas flowing at 1liter per minute.

In order to avoid the effects of phosphorus being out diffused from theregions 112 in the formation of the epitaxial layer 114, it is usuallydesirable to diffuse a uniform p-ty-pe layer (not shown) over the wholesurface of the wafer 110, using gallium for example, prior to thephosphorus diffusion.

The remaining oxide layer is etched away with hydrofluoric acid and anepitaxially grown layer 114 is produced of n-type silicon having aresistivity of about 3 to 30 ohm-centimeters and a thickness ofapproximately 0.5 mil. To accomplish this, the silicon is placed in thereaction zone of a growth furnace and subjected to a surface cleaningtreatment by pure hydrogen gas at about 1230 C. for 30 minutes. Theatmosphere is then changed to a mixture of hydrogen and silicontetrachloride, the latter at a partial pressure of 13 millimeters ofmercury, and growth is allowed to proceed for about 40 minutes at about1230 C. Under these conditions the growth rate has been found to beabout 0.3 micron per minute. After the formation of the epitaxial layer114 of a thickness of 12 microns, the wafer is again oxidized, andgallium is diffused for about minutes at 1125 C. from galliumsesquioxide at 900 C. with hydrogen as the reducing atmosphere.

Then the oxide layer is selectively etched on the polished side toexpose the silicon at the areas for the transistor emitter and junctionbridging areas. Then the exposed emitter areas are covered with waxresist coating and the bridging areas alone etched with a mixture ofnitric and hydrofluoric acids to a depth of 0.2 mil after removal of thewax resist. Phosphorus is then diffused into the emitter and bridgingareas for 20 minutes at 1075 C. from a phosphorus pentoxide source at310 C. using dry oxygen as the carrier gas. Thereafter the oxide isremoved from the surface and by use of a photoresist mask all areas ofthe surface are covered except those to which ohmic contacts are to bemade. Then a film of aluminum approximately 0.5 micron thick isevaporated over the entire surface. The photoresist and the undesiredaluminum thereon is removed using trichloroethylene solvent. Aphotoresist etch mask to enable a mesa to be formed is applied andetching carried out to a depth of 0.3 to 0.4 mil. Then the collectorareas of the mesa areas are coated with a wax mask and further 7 etchingcontinued to a depth of 0.2 to 0.3 mil. This etching forms transistor,diode and resistor mes as and also isolation slots where needed.

The above fabrication process has been successfully used for theformation of devices. Modifications of times, temperatures and otherparameters can be made if necessary or as desired.

It will be noted that after the formation of the epitaxially grown layer114 the fabrication may proceed as with previous functional electronicblocks.

Tests have been made on the response of conventional stroke gates andstroke gates formed in accordance with this invention. It has been foundthat the response to input pulses in identical test circuits shows thatthe epitaxially grown unit responds in a time about 1/5 that for aconventional unit. Further improvement in device performance alsoresults from the reduction of the saturation resistance in thetransistors areas.

While the present invention has been shown and described in certainforms only, it will be obvious to those skilled in the art that it isnot so limited but is susceptible to various changes and modificationswithout departing from the spirit and scope thereof.

What is claimed is:

1. A method of making a monolithic semiconductor device including thesteps of: diffusing, into at least one select portion of a first majorsurface of a body of semiconductive material of a first type ofsemiconductivity, a first pattern of at least one region of a secondtype of semiconductivity, while limiting the extent of said surface thatis exposed to dopant during the diffusing of said first pattern so saidat least one region is of small area compared with said surface; growingepitaxially a layer of second type semiconductivity material over saidfirst major surface and said first pattern of regions; diffusing asecond pattern of a plurality of spaced regions of said first typesemiconductivity into a surface of said epitaxially grown layer remotefrom said first pattern, said second pattern including a region oppositesaid at least one region of said first pattern of regions; diffusing athird pattern of regions of said second type semiconductivity in selectregions of said second pattern of regions, including said regionopposite said at least one region of said first pattern, to form aplurality of electronic functional elements.

2. A method of making a monolithic semiconductor device capable ofperforming the function of a circuit of separate components whichinclude at least one transistor and one resistance, said methodincluding the steps of: obtaining a substrate of semiconductive materialof a first type of semiconductivity having a resistivity of at leastabout 100 ohm-centimeters, said substrate having opposing majorsurfaces; forming by vapor diffusion a first region of a second type ofsemiconductivity in a first of said major surfaces having a sheetresistivity of from about 1 ohm per square to about ohms per square toprovide the function of a transistor collector region; forming byepitaxial growth a layer of said first type of semiconductivity oversaid first major surface, including said first region, having aresistivity of from about 1 ohmcentimeter to about 100 ohm-centimetertoform a p-n junction with said substrate to provide substantialelectrical isolation in said device by reason of said p-n junctionlimiting conduction normal to said major surface and the relatively highresistivity of said layer and said substrate limiting conductionparallel to said major surface, said layer having a thickness of fromabout 10 microns to about 20 microns so as to make little contributionto transistor saturation resistance; forming by vapor diffusion at leasttwo second regions of said first type of semiconductivity in the surfaceof said layer remote from said substrate, one such region being oppositesaid first region to provide the function of a transistor base regionand the other region to provide the function of a resistance; forming byvapor diffusion a third region of said second type of semiconductivityin the exposed surface of said second region providing a transistor baseregion to provide the function of a transistor emitter region.

'3. A method of making a monolithic semiconductor device in accordancewith claim 3 including the additional step of: shorting the junctionbetween said layer and said second region providing a resistance at apoint remote from said regions providing transistor functions so as toavoid injection of minority carriers into said layer upon application ofa potential at said point.

4. The subject matter of claim 1 further comprising: introducing, duringthe epitaxial growing of said layer, a quantity of doping impurity toprovide a doping impurity concentration therein appreciably lower thanthat of said at least one region of said first pattern; applying ohmiccontacts to regions of said second and third patterns; and retainingsaid plurality of electronic functional elements united by said body ofsemiconductive material.

5. The subject matter of claim 4 wherein: during said diffusing of saidthird pattern, at least one additional region of said second type ofsemiconductivity is diffused in a portion of said surface of said layernear said at least one region of said first pattern, said at least oneadditional region having appreciably greater impurity concentration thansaid layer and an ohmic contact is also applied to said at least oneadditional region; all of said diffusing operations are limited inextent to leave remaining material of said layer as grown withoutsignificant additional diffused impurities immediately adjacent saidregions of said second pattern.

6. The subject matter of claim 5 wherein: the diffusing of said thirdpattern of regions is performed in less than all of said regions of saidsecond pattern.

7. The subject matter of claim 1 further comprising: removing portionsof said layer, while retaining physical unity in the structure, theremoved portions being spaced from those portions in which said secondpattern of regions is diffused.

8. The subject matter of claim 1 wherein: the impurity used in thediffusing of said first pattern of regions is a member of the groupconsisting of phosphorus and arsenic.

9. The subject matter of claim 8 wherein: the impurity is phosphorus andprior to diffusing it, said surface of said body is diffused withgallium.

References Cited by the Examiner UNITED STATES PATENTS 3,149,395 9/1964Bray et al l48-175 3,152,928 10/1964 Hubner 14833.5 3,165,811 1/1965Kleim-ack et al l48175 3,211,972 10/1965 Kilby et al. 317235 HYLANDBIZOT, Primary Examiner.

DAVLD L. RECK, Examiner.

N. F. MARKVA, Assistant Examiner.

1. A METHOD OF MAKING A MONOLITHIC SEMICONDUCTOR DEVICE INCLUDING THESTEPS OF: DIFFUSING, INTO AT LEAST ONE SELECT PORTION OF A FIRST MAJORSURFACE OF A BODY OF SEMICONDUCTIVE MATERIAL OF A FIRST TYPE OFSEMICONDUCTIVITY, A FIRST PATTERN OF AT LEAST ONE REGION OF A SECONDTYPE OF SEMICONDUCTIVITY, WHILE LIMITING THE EXTENT OF SAID SURFACE THATIS EXPOSED TODOPANT DURING THE DIFFUSING OF SAID FIRST PATTERN SO SAIDAT LEAST ONE REGION IS OF SMALL AREA COMPARED WITH SAID SURFACE; GROWINGEPITAXIALLY A LAYER OF SECOND TYPE SEMICONDUCTIVITY MATERIAL OVER SAIDFIRST MAJOR SURFACE AND SAID FIRST PATTERN OF REGIONS; DIFFUSING ASECOND PATTERN OF A PLURALITY OF SPACED REGIONS OF SAID FIRST TYPESEMICONDUCTIVITY INTO A SURFACE OF SAID EPITAXIALLY GROWN LAYER REMOTEFROM SAID FIRST PATTERN, SAID SECOND PATTERN INCLUDING A REGION OPPOSITESAID AT LEAST ONE REGION OF SAID FIRST PATTERN OF REGIONS; DIFFUSING ATHIRD PATTERN OF REGIONS OF SAID SECOND TYPE SEMICONDUCTIVITY IN SELECTREGIONS OF SAID SECOND PATTERN OF REGIONS, INCLUDING SAID REGIONOPPOSITE SAID AT LEAST ONE REGION OF SAID FIRST PATTERN, TO FORM APLURALITY OF ELECTRONIC FUNCTIONAL ELEMENTS.